High voltage and high power semiconductor integrated circuit devices require unusual isolation structures to provide effective electrical isolation between adjacent devices in the semiconductor substrate. A common technique is to form buried oxide tubs around a silicon substrate region. The typical fabrication method is to etch deep trenches in a single crystal silicon substrate, oxidize the silicon in the trenches, and deposit a thick layer of polysilicon over the etched silicon surface. The polysilicon layer serves as the substrate or "handle" for the wafer during subsequent processing to form the integrated circuit. The bottom surface of the single crystal silicon wafer is polished away to reveal the oxide trenches thus leaving isolated islands of single crystal silicon in the polysilicon handle wafer.
More recently, techniques have become available for hydrophilic bonding of silicon wafers. Using this technique, an isolating layer is formed on the surface of one of the silicon wafers and that surface is bonded to another silicon wafer, thus forming a two wafer "sandwich" with an isolating layer there between. Isolation trenches are then formed through the thickness of the device wafer with the trenches essentially encircling and isolating silicon regions of the device wafer. In an implementation of the well known dielectric isolation technique, the isolation layer is an oxide layer, as described in U.S. Pat. No. 5,478,758. An alternative approach is to use a junction isolation layer, i.e. a heavily doped layer, as the isolation layer. In this approach the bond for the bonded wafer is silicon to silicon which is easily implemented using hydrophilic bonding. In both cases the surfaces being bonded are highly polished.
In bonded wafer technology in general, the gettering of impurities has been a manufacturing and performance issue. Impurities that originate from the interface are a source of contamination in the finished device. It is also predictable that a substantial source of device contamination results from impurities present during the wafer bonding operation, and in particular, impurities that originate from the handle wafer. Backside gettering as generally used in semiconductor technology is ineffective with bonded wafers due to the thickness of the bonded structure and the presence of the barrier at the bonded wafer interface. Thus, as described in the patent referenced above, front side gettering from gettering layers formed in the side trenches on the device side of the bonded wafer is typically the method of choice. However, it is evident that the front side gettering approach of the patent cited above is ineffective for gettering impurities at this early stage of wafer production.
It would beneficial to remove the handle wafer as a source of contamination and to getter impurities from the wafers being bonded at an early stage in the manufacturing operation, i.e. before the bonded interface is formed.